This invention relates to a computer method and apparatus for transferring data between a processor section, i.e. a host processor, and an I/O section, i.e. one or more peripheral units or input/output units.
More particularly, this invention provides an I/O controller that can transfer multiple-byte blocks of data, in what is known as a direct memory access (DMA) transfer, and that can execute a processor commanded transfer, designated a PIO transfer, with high time efficiency.
I/O controllers are known for providing both processor commanded transfers, i.e. PIO transfers, and multiple-byte block transfers, i.e. DMA transfers. In general, a PIO transfer is executed in response to a command from the local processor in the I/O controller and transfers a word or other unit of information between the local processor and a designated I/O unit. The execution of a PIO transfer typically is brief, for example requiring approximately five microseconds in a systems operating with a sixteen megahertz clock. A direct memory access transfer, on the other hand, transfers a significantly larger quantity of data, typically designated as a block having a specified number of bytes, between the main storage unit of the host processor and a designated I/O unit. DMA transfer rates are approximately four megabytes per second in systems operating with a sixteen megahertz clock.
It is desirable, for time-wise efficient operation, i.e., a high system speed, that DMA transfers be executed promptly. It likewise is desirable that PIO transfers be executed promptly. In addition, it is preferable that PIO transfers are executed immediately, without waiting for the completion of an in-process DMA transfer, which could take several milliseconds. For example, if a DMA transfer were underway to one disk drive address, this could hold up a pending PIO to another disk drive address. For example, if the main system directed an I/O controller to send a command to another disk drive, the I/O controller would have to wait until the end of the DMA transfer. At the same time, however, it is inefficient to abort a DMA transfer in order to accommodate a PIO transfer and then require restarting of the same DMA transfer.
Among the known I/O controllers that handle both DMA transfers and PIO transfers are the model XA2000 computer systems of Stratus Computer, Inc., and the techniques disclosed in U.S. Pat. Nos. 4,926,315; No. 4,309,754; and No. 4,371,932. The noted U.S. Pat. No. 4,371,932 provides an interleaving mechanism that enables host processor direct program control data transfers to be performed on a cycle steal basis when the I/O controller is executing data transfers for a block of data. The patent describes a dual port random access storage mechanism to provide temporary storage in executing the DMA and the PIO data transfers.
It is an object of this invention to provide an improved method and apparatus for the transfer, between a host processor and multiple I/O units in a digital data processing system, of data on both a direct memory access basis and a processor command basis with high time-wise efficiency.
Another object is to provide such a method and apparatus for providing both DMA and PIO transfers with minimal wait for PIO transfers and minimal delay for DMA transfers.
It is a further object of the invention to provide an I/O controller that interleaves PIO-type transfers with DMA-type transfers with minimal delay for both kinds of transfers.
Other objects of the invention will in part be obvious and will in part appear hereinafter.